Lead on chip semiconductor memory device with multiple bit configuration
US5880531A · kind A · utility
7Cited by
12References
20Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Nov 19, 1997 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Nov 19, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having inner lead portions of a plurality of leads disposed through at least one insulating film on a semiconductor chip and electrically insulated from the semiconductor chip, includes bonding pads for at least data input/output arranged in two rows axially symmetrically in a substantially central portion of the semiconductor chip interposed between memory arrays and bonding wires for connecting the inner lead portions and the bonding pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.