Apparatus and method for configuring integrated circuit option bits with different bonding patterns
US5880596A · kind A · utility
20Cited by
7References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 28, 1997 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Feb 28, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is an integrated circuit design and method which provides optional configurations depending upon the connection of optional bond wires. The design retains the flexibility of the IC's mode of operation through the fabrication and testing of the wafers, until the packaging of the IC. ICs designed in accordance with the present inventions also provide advantages of size, efficiency and reliability over those previously known.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.