Device for interfacing logic signals from the LLL level to the TTL and CMOS level
US5880600A · kind A · utility
1Cited by
7References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 1995 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Sep 25, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device for interfacing from the LLL level to the TTL and CMOS level that comprises, in cascade, a first and a second amplifier-inverter and a shaping circuit delivering an inverted logic signal at the TTL level. A power inverter-amplifier circuit receives the inverted logic signal at the TTL level and delivers an amplified logic signal at the TTL level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.