Reset circuit using comparator with built-in hysteresis
US5880611A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 25, 1997 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Jul 25, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2017/226
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparator with a built-in offset is disclosed. The claimed comparator includes a bias current circuit, a differential input stage with the built-in of-set, and a hysteresis circuit. The built-in offset is generated by using a resistor in the differential input stage of the comparator such that the resistor is driven by the bias current as well as the current generated by the hysteresis circuit. Additionally, a reset circuit which uses the comparator with the built-in offset is claimed. The reset circuit uses a voltage divider circuit to divide a first input voltage to the comparator. A band-gap voltage reference is used to provide a second input voltage to the comparator. Therefore, the reset circuit generates a reset signal when the divided voltage reaches the value of the band-gap voltage plus the offset. In another embodiment, a comparator having a differential input stage, an output stage, and a bias circuit with a hysteresis circuit is disclosed. The hysteresis circuit selectively applies a bias voltage to the differential input stage to achieve the hysteresis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.