Power supply control techniques for FET circuits
US5880623A · kind A · utility
17Cited by
5References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 28, 1997 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Feb 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/247
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
Method and circuitry for power control in integrated circuits using field effect transistor (FET) technology are disclosed. According to the present invention, for each circuit block that is biased by the power supply voltage a dedicated level shifter is inserted between the block and the power supply. In one embodiment, a switch is also coupled in parallel to the level shifter. The switch is closed when a low external power supply voltage is applied, and opened when a higher power supply voltage is applied. A second embodiment removes the switch and adds a bias generator that supplies a bias voltage to each level shifter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.