Burn-in stress control circuit for a semiconductor memory device
US5881004A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 2, 1997 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | May 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A burn-in stress control circuit for an integrated memory device, such as DRAM, includes a first logic gate for receiving a burn-in enable signal and outputting an inverted burn-in enable signal, a resistor having a first terminal connected to the input terminal of the first logic gate, a first capacitor connected between the second terminal of the resistor and ground. A first transistor having a control terminal connected to the second terminal of the resistor and a first main terminal connected to a source voltage, is activated only when the burn-in enable signal is a high logic signal, thereby outputting the source voltage to a second main terminal of the first transistor. A second transistor having a control terminal connected to an output terminal of the first logic gate, a first main terminal connected to ground and a second main terminal connected to the second main terminal of the first transistor, is activated only when the burn-in enable signal is a low logic signal. Thus, peak current applied to a memory cell array, and noise can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.