Multiple transistor dynamic random access memory array architecture with simultaneous refresh of multiple memory cells during a read operation
US5881010A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 1997 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | May 15, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A four transistor dynamic memory cell architecture and refresh technique which allows for cell refresh to occur during a read operation. The access and memory transistors of the individual memory cells are fabricated with a relative width-to-length ratio such that it is sufficient to merely activate the associated word line to perform the refresh operation. This is accomplished without activating the read sense amplifier resulting in lower power consumption and the retention of most recently read data. Multiple word lines may be activated concurrently utilizing the technique disclosed to further reduce the refresh rate overhead in a memory array and increase the overall memory array bandwidth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.