Centralized performance monitoring architecture
US5881223A · kind A · utility
34Cited by
7References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 1996 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Sep 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamically configurable arrangement for determining performance of a microprocessor. A plurality of functional units in a microprocessor are coupled to a performance counter, wherein the performance counter is incremented in response to occurrence of a predetermined event. A plurality of repeaters coupled between the plurality of functional units and the performance counter. Control circuitry coupled to the plurality of repeaters, wherein the control circuitry selectively enables the repeaters such that only one functional unit is coupled to the performance counter at a particular time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.