Host adapter system including an integrated PCI buffer controller and XOR function circuit
US5881250A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 15, 1996 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Mar 15, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/387
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A host adapter system includes a secondary computer bus, a plurality of I/O buses, and a plurality of host adapter circuits. Each host adapter circuit is connected to the secondary computer bus and to one I/O bus in the plurality of I/O buses. An integrated buffer controller and data function circuit is connected to the secondary computer bus and an external buffer memory. The external buffer memory appears to the plurality of host adapter circuits as a host computer buffer memory. The integrated buffer controller and data function circuit includes a data function circuit that is controlled by addresses supplied to the circuit. The integrated buffer controller and data function circuit has a bus interface that is used to connect the circuit to the secondary computer bus. A data channel in the integrated buffer controller and data function circuit connects the bus interface to a buffer memory controller. The buffer memory controller has a buffer memory port that is connected to the external buffer memory. The integrated buffer controller and data function circuit includes a slave data channel and a master data channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.