Method and apparatus for sequencing and decoding variable length instructions with an instruction boundary marker within each instruction
US5881260A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 1998 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Feb 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are shown for decoding variable length instructions in a processor where a line of variable length instructions from an instruction cache are loaded into an instruction buffer and the start bits indicating the instruction boundaries of the instructions in the line of variable length instructions is loaded into a start bit buffer. A first shift register is loaded with the start bits and shifted in response to a lower program count value which is also used to shift the instruction buffer. A length of a current instruction is obtained by detecting the position of the next instruction boundary in the start bits in the first register. The length of the current instruction is added to the current value of the lower program count value in order to obtain a next sequential value for the lower program count which is loaded into a lower program count register. An upper program count value is determined by loading a second shift register with the start bits, shifting the start bits in response to the lower program count value and detecting when only one instruction remains in the instruction buffer. When one instruction remains, the upper program count value is increme…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.