Arbitration system based on requester class and relative priority including transmit descriptor valid bit for a shared resource having multiple requesters
US5881313A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 1994 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Nov 7, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with principles of the invention, there is provided an arbitration system for multiple requesters of a shared data transfer resource, such as a system bus or a peripheral bus. The disclosed system arbitrates among multiple classes of requesters which are divided into multiple levels of a request hierarchy. In the example embodiment, the multiple requesters include logic for processing received data from the network, logic for processing data to be transmitted onto the network, logic for moving transmit and receive descriptors between the host memory and the adapter, logic for reporting status from the adapter to the host, and logic for generating an error and maintenance status update from the adapter to the host. The new system ensures fairness between transmit and receive processes, that FIFOs associated with transmit queues are not underrun, and further that notification of non-error and maintenance status changes are processed with minimal latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.