Method of manufacturing semiconductor device with reduced charge trapping
US5882961A · kind A · utility
12Cited by
19References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1997 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Sep 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/671
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device (20) is fabricated by doping a dielectric layer (29) located over the surface of a semiconductor substrate (21). The dielectric layer (29) contains nitrogen and is doped with silicon ions by using an ion implantation process (15) such that a peak concentration (32) of the silicon ions remains in the dielectric layer (29) during the ion implantation process (15). Doping the dielectric layer (29) reduces charge trapping in the dielectric layer (29) and reduces power slump in the semiconductor device (20) during high frequency operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.