Vertical insulated gate FET
US5883411A · kind A · utility
22Cited by
8References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1992 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Nov 23, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
An insulated gate FET such as a power MOS FET is made by forming a rectangular parallelepiped-shaped recess in a direction that the side walls of the recess make 45.degree. angle against the <100> direction of the silicon substrate having (100) plane as principal surface, and the vertical side walls of (010) or (001) planes are used as channel region of the insulated gate FET, thereby assuring a large electron mobility in the channel, hence low channel resistance suitable for high power operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.