Semiconductor device with particular silicide structure
US5883418A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 11, 1997 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Jun 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A silicide layer having a two-layer structure or a silicide layer made of material having high etching selectivity is formed on a silicon layer constituting a gate electrode, causing the silicide layer to serve as an etching stopper at the time of forming a contact hole. Furthermore, a top surface of an insulating layer in which a contact hole is formed is planarized by a CMP method, facilitating subsequent formation of an interconnection or the like. In addition, when a silicide layer consisting of two layers is formed on the gate electrode, each of those two layers can be made of either the same material or materials different from each other. Thus, even if contact holes extending to the gate electrode and source/drain regions are simultaneously formed in the planarized insulating layer, lower layers of the gate electrode and the source/drain regions will not be etched, resulting in a semiconductor device in which an interconnection on the insulating layer can be formed easily.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.