Clock signal generating device having a redundant configuration
US5883533A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1996 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Sep 26, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A clock signal generating device of the present invention has an active and a spare clock selecting circuit. The two clock selecting circuits each includes a selector for selecting one of a plurality of outside timing signals and outputting it as an inside clock signal under the control of a controller. A PLL (Phase Locked Loop) circuit is commonly connected to the outputs of the active and spare selecting circuits. The PLL circuit reduces the influence of switching between the active and spare selecting circuits and switching between the outside timing signals. The PLL circuit includes a hold-over circuit for temporarily holding, in response to a control signal fed from the controller, a signal output from the selecting circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.