Method for generating an improved model for evaluating the operation of an integrated circuit design
US5883818A · kind A · utility
13Cited by
18References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 1996 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Aug 29, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Modeling of propagation delay and output transition time by use of fitting functions comprised of standard Taylor series and inverse powers is disclosed. These components are used as a basis for generating an equation that predicts circuit performance over a wide range of input transition and output capacitive loads. The present invention includes a computer implemented method for adding functions to the fitting functions or removing functions from the fitting functions until an acceptable error limit has been reached.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.