Parallel adding and averaging circuit and method
US5883824A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 1993 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Nov 29, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus that can also be used for generating the average of two integers. The apparatus can be divided into a plurality of sub-adders that operate on sub-words of the input integers in parallel. Hence, the adder can be used for adding or subtracting one set of two integers wherein each integer is of some predetermined length or a plurality of sets of two integers provided the sum of the lengths of the integers is less than or equal to this predetermined length. The apparatus can also generate the sum, or difference, of each of the sub-words divided by two. The parallel operations can be carried out in response to a single instruction. The results of the division by two are rounded in a manner that eliminates biasing of the results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.