Semiconductor memory device and a reading method thereof
US5883851A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 1998 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Mar 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device, there is provided a column detecting circuit for generating a detection signal DETIO when respective voltage levels on a pair of I/O lines IO and IOB are developed into predetermined voltage levels which can be sensed as a valid data by external circuitry. Thereafter, a block selecting circuit and a sensing control signal generating circuit are respectively disabled by the detection signals DETIO and DETIOB causing a bit line precharge operation to be performed during a reading operation Thus, the sensing consumed by sense amplifiers during the reading operation period is reduced. In addition, since the bit line precharge operation is performed during the reading operation period, the bit line precharge time is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.