Architecture for an I/O processor that integrates a PCI to PCI bridge
US5884027A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1997 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Jun 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-functional device that integrates a high performance processor into a PCI to PCI bus bridge. The invention consolidates a high performance processor, a PCI to PCI bus bridge, PCI bus-processor address translation unit, direct memory acces's (DMA) controller, memory controller, secondary PCI bus arbitration unit, inter-integrated circuit (I.sup.2 C) bus interface unit, advanced programmable interrupt (APIC) bus interface unit, and a messaging unit into a single system which utilizes a local memory. The PCI bus is an industry standard high performance, low latency system bus. The PCI to PCI bridge provides a connection path between two independent 32-bit PCI buses and provides the ability to overcome PCI electrical loading limits. The addition of the local processor brings intelligence to the PCI bus bridge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.