Processor which performs dynamic instruction scheduling at time of execution within a single clock cycle
US5884060A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1997 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Mar 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for scheduling the execution of one or more of a sequence of instructions for superscalar execution by a central processing unit during a single clock cycle of the processor clock is disclosed wherein the scheduling process is performed in a manner which does not dictate the duration of the processor clock period. During the decode stage of the processor pipeline, the instructions are classified, decoded, and data and resource dependencies are detected and resolved for operand access, with these processes being performed virtually in parallel so that the instructions can be appropriately scheduled for execution at the beginning of the next processor clock cycle. Because of the parallel nature of the scheduling process, scheduling can be performed and completed fast enough that processes other than instruction scheduling will dictate the minimum processor clock period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.