Data retiming circuit
US5886552A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | May 20, 1997 |
| Grant date | Mar 23, 1999 |
| Priority date | — |
| Expiry date | May 20, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0338
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An improved data retiming circuit which is capable of more effectively retiming an externally inputted data by using a plurality of clocks from a voltage controlled oscillator of a phase-locked loop. The circuit includes a first delay unit for increasing a rising and falling time from an externally inputted data by a predetermined time as much as a clock phase difference, a first data latch unit connected so that the phase from the clock generator can be to correspond with the number of different clocks for latching the data inputted in accordance with the clock, a second delay unit for receiving the data from the first delay unit and for delaying the data so that a clock is selected and coincides with the timing until the output of the clock, a data latch state determination unit for determining the logic signal state of the data latched by the first data latch unit in an analog method, a clock selection unit for logically compares a plurality of clocks inputted and a data state signal outputted from the data latch state determination unit and for selecting a retiming signal, and a second data latch unit for latching the data relayed by the second delay unit in accordance with the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.