High voltage charge transfer stage
US5886566A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 1997 |
| Grant date | Mar 23, 1999 |
| Priority date | — |
| Expiry date | Aug 21, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/247
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An improved charge transfer stage with an expanded output voltage range and high charge transfer efficiency is described. The charge transfer stage can be implemented as an output stage in a four phase clock negative charge pump system. The charge transfer stage comprises a PMOS pass transistor coupling the transfer stage input and output, a resistor between the transfer stage input and the pass transistor gate, a clock terminal, a capacitor configured PMOS transistor coupling the clock terminal to the gate of the pass transistor, and a diode from the transfer stage output to ground. When the transfer stage input goes low, charge is coupled through the resistor to pre-charge the gate of the pass transistor. The resistor has a higher junction breakdown voltage than a transistor which allows the gate of the pass transistor to be driven to a larger voltage. To provide sufficient charge to turn on the pass transistor, a logic high level greater than the power supply, such as 2 VCC, can be used for the clock signal coupled through the capacitor configured transistor to the gate of the pass transistor. To prevent the 2 VCC logic high level from forward biasing the p-n junction formed by …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.