Bit interleaving in a memory which uses multi-bit DRAMs
US5886930A · kind A · utility
12Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1997 |
| Grant date | Mar 23, 1999 |
| Priority date | — |
| Expiry date | Sep 24, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage apparatus including a memory; a first buffer into which data words are read from said memory; and a word selector receiving on a first input data words from the buffer and on a second input data words from another source, and producing on an output for storage back into the memory data words that are selected from the first and second inputs to the word selector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.