Synchronous digital communication system with a hierarchical synchronization network
US5886996A · kind A · utility
18Cited by
8References
3Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 15, 1995 |
| Grant date | Mar 23, 1999 |
| Priority date | — |
| Expiry date | Dec 15, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J2203/0089
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In synchronous digital communication systems using a synchronization quality marker (SSM), timing loops can be created. To avoid such timing loops, a synchronous digital communication system is provided having network elements (NE11, . . . , NE33) in which two classes (top, bottom) are defined for interface units (S.sub.1, . . . , S.sub.x, . . . , S.sub.X+i).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.