Methods and apparatus for error correction
US5887005A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 26, 1997 |
| Grant date | Mar 23, 1999 |
| Priority date | — |
| Expiry date | Jun 26, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/151
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error correction decoder which includes a syndrome calculator, an error locator polynomial calculator, a standard error locator polynomial calculator, an error transform calculator and an inverse error transform calculator. These error correction decoder calculators provide a pipelined architecture for performing Reed-Solomon error correction calculations quickly. In the inverse error transform calculator, a method for calculating inverse error transforms is used. The method is adapted to receive error transforms in the same sequence as the error transforms are output by the error transform calculator without the need for buffering between the error transform calculator and the inverse error transform calculator and without the addition of substantial timing delays. In particular, the inverse error transform calculator is adapted to receive error transforms in the sequence E.sub.0, E.sub.1 . . . E.sub.N-1. The inverse error transform calculator is adapted to calculate inverse error transforms using the equation ##EQU1## In one embodiment, the inverse error transform calculator implements the method using a semiconductor device having adders, multipliers, memory elements and a re…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.