Methods and apparatus for error correction
US5887006A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 26, 1997 |
| Grant date | Mar 23, 1999 |
| Priority date | — |
| Expiry date | Jun 26, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/47
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error correction decoder which includes a syndrome calculator, an error locator polynomial calculator, a standard error locator polynomial calculator, an error transform calculator and an inverse error transform calculator. These error correction decoder calculators provide a pipelined architecture for performing Reed-Solomon error correction calculations quickly. The error transform calculator includes a plurality of error transform processing circuits. The error transform calculator uses multiplexors to provide an adaptive input mechanism that adapts to receive known error transforms in an appropriate one of the error transform processing circuits. The multiplexors are used to form appropriate shift and feedback paths that are adapted to calculate unknown error transforms from the received known error transforms. The calculations are performed using multipliers and adders. Memory elements that store coefficients of a standard error locator polynomial are also used. An AND gate path is formed by coupling a plurality of AND gates in series. The AND gate path is used to provide simple and efficient control of the error transform calculator using coefficients of the standard error…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.