Introducing processing delay as a multiple of the time slot duration
US5887037A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1996 |
| Grant date | Mar 23, 1999 |
| Priority date | — |
| Expiry date | Feb 27, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B7/0851
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An apparatus for performance improvement of a burst mode digital wireless receiver has a processing circuit for processing a plurality of received signals and providing a processed signal and a delay circuit for introducing a predetermined delay to the processed signal. The delay circuit is coupled to the processing circuit. The predetermined delay is such that the processed signal is delayed to correspond with a later data burst. The processing circuit weights and combines the received signals, where the processing circuit reduces a mean squared error of an output signal. The processing circuit weights and combines the received signals using a predetermined symbol pattern within a sync sequence within a time slot.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.