Condensed single block PLA plus PAL architecture
US5889412A · kind A · utility
1Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 20, 1997 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | Jun 20, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17708
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A condensed single block plus PLA architecture utilizing a rectangular shape is shown. By interleaving the ORterms of the PLA array with the Pterms of the array, a significant amount of die space is saved when incorporating the circuit with silicon. The decode routing required is now simplified and the propagation delay skews through the array are also reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.