Voltage step-up circuit
US5889427A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 19, 1996 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | Apr 19, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0036
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A parallel connection of an enhancement type nMOS transistor and an enhancement type pMOS transistor is connected between an input terminal receiving a clock signal and a capacitor. The pMOS transistor is turned on and off in dependece on an output of a power supply voltage detector, so that a signal transmission path between the input terminal and the capacitor, as the clock signal is at a high level, has a switched position at a side of the nMOS transistor when the power supply voltage is high, and a switched postiion at a side of the pMOS transistor when the power supply voltage is low. Due to a threshold drop effect of the nMOS transistor, a signal amplitude of a high level is limited to an output level of a limiter minus a threshold voltage of the nMOS transistor, reducing a charge-discharge current of the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.