Phase-locked loop with capacitive voltage divider for reducing jitter
US5889439A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 1997 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | Aug 20, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a phase-locked loop comprising a phase detector (1), a loop filter (5) and a controlled oscillator (17) which are arranged on a common integrated circuit, interferences coupled into the substrate of the integrated circuit by other parts of the circuit are suppressed. In a first embodiment of the invention, this object is achieved in that the controlled oscillator (17) is preceded by a capacitive voltage divider (9) which comprises at least two capacitances (10, 12), the controlled oscillator (17) is controlled in dependence upon the output signal of the capacitive voltage divider (9), and the capacitive voltage divider (9), together with the phase detector (1), the loop filter (5) and the controlled oscillator (17) is arranged on an integrated circuit. In accordance with a second embodiment of the invention, the reduction of interference is achieved in that the controlled oscillator (17) has a differential structure and comprises at least two voltage-controlled current sources (18, 19) whose circuits are coupled to a power supply potential and to a substrate on which the integrated circuit is arranged, the controlled oscillator (17) has an output stage (20) which is arranged beh…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.