Memory requirement reduction in a SQTV processor by ADPCM compression
US5889562A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 1997 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | Mar 4, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/98
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An SQTV processor is for converting a video signal received at an interlaced scanning frequency of 50 or 60 Hz to an interlaced scanning frequency of 100 or 120 Hz, respectively, and implementing algorithms for noise filtering and of edge definition. The process includes: an analog-digital converter (ADC) of analog input signals of luminance and chrominance; at least a field memory (FIELD MEMORY.sub.-- 1), or more preferably two similar field memories, where digital blocks of luminance (Y) value and blocks of values of each one of the two chrominance (U, V) components of the converted video signals are stored; one "First-In-First-Out" (LINE MEMORY) register for digital values read from the field memory containing the pixels of a whole line of each field; a noise filtering block (NOISE REDUCTION); a sampling frequency converter (SRC) of the fields from 50 or 60 Hz to 100 or 120 Hz; a conversion circuit for the vertical format (VFC), an edge definition (PE) enhancement circuit; and a digital-to-analog converter (DAC) of the processed luminance and chrominance (YUV) signals. The processor further includes a compressing and coding circuit for the converted video signals according to an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.