Processing system with memory arbitrating between memory access requests in a set top box
US5889949A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 11, 1996 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | Oct 11, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N11/20
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for providing memory arbitration which allows multiple hardware functions implemented in a single ASIC to utilize a single shared memory unit or multiple shared memory units. The memory arbitration technique establishes a priority among multiple memory access requesters and is particularly well-suited for use in a set top box processing system. A plurality of memory access requests are received from a plurality of processing elements in a set top box processing system. The processing elements include a transport stream demultiplexer, a host central processing unit and a graphics processor. The processing elements are permitted to access a shared memory in accordance with an established priority. The established priority assigns a higher priority to the graphics processor than to the host central processing unit, and may be in the order of graphics processor, transport stream demultiplexer, and central processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.