Patent · US Expired

Logical bus structure including plural physical busses for a multiprocessor system with a multi-level cache memory structure

US5889969A · kind A · utility

7Cited by

2References

12Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Klaus J. Getzlaff · Schenefeld, DE
Bernd Leppla · Meiningen, DE
Hans-Warner Tast · Holzgerlingen, DE
Udo Wille · Holzgerlingen, DE

Key dates

Filing date	Nov 27, 1996
Grant date	Mar 30, 1999
Priority date	—
Expiry date	Nov 27, 2016

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/1657
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An improved multiple bus system for a multiprocessor computer system is disclosed for a computer system having a multiple level cache memory structure. The system includes one or more logical busses each including two or more physical busses for coupling multiple processors to a memory unit. Each logical bus is coupled to a bus switching unit which in turn couples all of the processors in the multiprocessor system to a memory unit over the physical busses comprising the logical bus. The system further manages near end signal reception problems caused by multiple processors electrically interconnected over such a bus system.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.