Method and apparatus permitting the use of a pipe stage having an unknown depth with a single microprocessor core
US5889975A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 1996 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | Nov 7, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor core suitable for use with a wide variety of instruction fetch units. The processor core contains a plurality of pipe stages including an instruction pointer generation stage and a decode stage. The core bundles all control necessary for downstream pipeline operation with an instruction address in a first stage. The bundle is transmitted outside the core to the instruction fetch unit. The instruction fetch unit fetches the instruction and adds it to the bundle, before forwarding the bundle as modified back within the core and down the pipeline. In this way, an external pipe stage is introduced providing a connection between discontinuous pipe stages in the core. Additionally, by bundling the control signals and address information in a single bundle that traverses the external pipe stage as a group, synchronization concerns are reduced or eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.