Assembler system and method for a geometry accelerator
US5889997A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 30, 1997 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | May 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An assembler system enables efficient usage of space in a read only memory (ROM) that permits multiway instruction branching. Source code is analyzed and assembled by the assembler system and the assembler system then efficiently places the instructions in the ROM. The source code includes at least the following elements or an equivalent counterpart thereof: next state statements, nonaligned instructions, align statements, and aligned instructions. Next state statements serve as a flag to separate the various instructions. Nonaligned instructions are defined as those instructions that are nonaddressable by other instructions, i.e., those instructions that are not branched to. Align statements serve as a flag to the assembler system that a plurality k (where k is equal to 2.sup.n and where n is a positive integer) of aligned instructions directly follow in succession. Furthermore, aligned instructions are defined as those that are addressable by a plurality of other instructions, i.e., those instructions that can be branched to by a branch instruction. A branch instruction can be a nonaligned or an aligned instruction. The assembler system is configured to store the nonaligned instr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.