Interrupts between asynchronously operating CPUs in fault tolerant computer system
US5890003A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 1993 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | Sep 7, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.