Data processor incorporating a ferroelectric memory array selectably configurable as read/write and read only memory
US5890199A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 21, 1996 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | Oct 21, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1475
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor incorporating a memory array which is selectably configurable as either read/write or read only memory or the combination of both read/write and read only memory includes a memory mapper for receiving logical addresses from an arithmetic logic unit ("ALU") and converting the same to physical addresses within the memory array in accordance with configuration instructions stored in a local non-volatile memory. By utilizing a common memory technology for the memory array, such as non-volatile ferroelectric random access memory ("FRAM"), the proportions and layout of the memory array which may be utilized for MPU instructions and data may be selectably controlled. The use of a memory mapper also allows for the establishment of an effective password or encryption protection function for the memory array data of particular utility in conjunction with radio frequency identification ("RF/ID") transponders and other applications which must store sensitive data in non-volatile storage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.