Coherence apparatus for cache of multiprocessor
US5890217A · kind A · utility
87Cited by
8References
60Claims
0Family size
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Key dates
| Filing date | Feb 7, 1996 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | Feb 7, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.