Method and system for offset miss sequence handling in a data cache array having multiple content addressable field per cache line utilizing an MRU bit
US5890221A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1994 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | Oct 5, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interleaved data cache array which is divided into two sub arrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a first content addressable field containing a portion of an effective address for the selected block of data, a second content addressable field contains a portion of the real address for the selected block of data and a data status field. By utilizing two separate content addresssable fields for the effective address and real address offset and alias problems may be efficiently resolved. A virtual address aliasing condition is identified by searching each cache line for a match between a portion of a desired effective address and the content of the first content addressable field. The desired effective address is translated into a desired real address and a portion of the desired real address is then utilized to search each cache line for a match with the content of the second content addressable field if no match was found within the first content addressable field during the previous cycle. An offset condition is identified by …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.