Polysilicon TFT having exact alignment between the source/drain and the gate electrode
US5892246A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1997 |
| Grant date | Apr 6, 1999 |
| Priority date | — |
| Expiry date | Nov 19, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
The source-to-drain gap in a TFT is formed by exposing a positive photoresist from the back side of the substrate, using the gate as an optical mask. The resulting photoresist mask then protects the underlying amorphous silicon while the structure is exposed to a gaseous plasma that includes dopant material. Heavily doped regions are thus formed, leaving a gap that is in perfect alignment with the gate. After removal of the photoresist, the structure is given a laser anneal which results both in the crystallization of the amorphous silicon into polysilicon as well as a more even distribution of the dopant material. The structure is completed in the usual way by providing a passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.