Layout structure of capacitive element(s) and interconnections in a semiconductor
US5892266A · kind A · utility
2Cited by
4References
5Claims
0Family size
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Key dates
| Filing date | May 30, 1997 |
| Grant date | Apr 6, 1999 |
| Priority date | — |
| Expiry date | May 30, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/919
Abstract
The present invention reduces parasitic capacitance in a capacitive element distribution system by running unit electrode lead lines and common electrode lead lines in different directions so that the conductor lines may be sufficiently separated to suppress parasitic capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.