Matrix interpolation
US5892348A · kind A · utility
24Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1997 |
| Grant date | Apr 6, 1999 |
| Priority date | — |
| Expiry date | Jun 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T3/4007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of memory matrix interpolation in an ASIC processor requires a reduced amount of program code and memory space in the interpolation routine by shifting values in the interpolation routine between shift registers and overwriting redundant data in the shift registers with intermediate results. A switched reluctance drive system incorporating such a method provides similar advantages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.