Transistor protection circuit and method
US5892379A · kind A · utility
3Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1997 |
| Grant date | Apr 6, 1999 |
| Priority date | — |
| Expiry date | Jun 2, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit and method protect a transistor (68, 70) from damage when controlling an input signal (V.sub.PROG) that exceeds a gate to channel stress voltage of the transistor. A small, low current protection transistor (64, 66) is serially coupled to the gate electrode of the transistor being protected. The gate of the protection transistor is biased to a voltage (V.sub.P, V.sub.N) of lower magnitude than the input signal to limit the voltage applied to the gate of the protected transistor to a value within the stress voltage of the protected transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.