Mixed signal phase locked loop with process and temperature calibration
US5892406A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 1996 |
| Grant date | Apr 6, 1999 |
| Priority date | — |
| Expiry date | Oct 23, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A mixed signal phase locked loop is optimized for fast settling and low noise sensitivity. To this end, this device has a digital wide range delay line and a low gain per stage adjust. When first activated, the loop calibrates the digital delay line to its nominal delay characteristic. This delay line, together with the linear low gain per stage adjust, constitutes the internal oscillator of the phase locked loop. After achieving nominal delay, the oscillator uses the low gain per stage adjust to lock to a desired reference or a submultiple thereof. According to the preferred embodiment, the loop locks its internal 125 MHz oscillator to a 25 MHz reference. After achieving lock, the loop performs synchronous data recovery by locking to an incoming data stream, instead of the internal reference, and performing bit framing. In case of losing lock, the phase locked loop of the present invention is capable of recalibrating itself and regaining lock in under 3 microseconds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.