Scanning circuit and image display apparatus
US5892495A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1996 |
| Grant date | Apr 6, 1999 |
| Priority date | — |
| Expiry date | Oct 2, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/06
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A scanning circuit is provided with a plurality of address lines and AND circuits. The address lines respectively supply bit signals constituting an address signal and inverted bit signals, and each AND circuit conducts a logical operation on a predetermined number of bit signals and inverted bit signals selected from the bit signals and inverted bit signals supplied from the address lines. The AND circuits are connected to the address lines so that only one bit is switched when the address signal carries. Furthermore, a frequency of the least significant bit of the address signal is set to 1/4 of the dot frequency, while the two bits at the high end are set to have the same frequency and a phase difference of 90.degree. each other. With the described arrangement, a phase shift is prevented from occurring to an outputted signal when the address signal carries. Furthermore, the arrangement ensures that the scanning circuit can be realized in a simple circuit arrangement and operates at low frequencies, thereby ensuring a decrease in power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.