Potential difference transmission device and semiconductor memory device using the same
US5892723A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1997 |
| Grant date | Apr 6, 1999 |
| Priority date | — |
| Expiry date | Apr 14, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device 200 includes: a memory cell array 101 including a plurality of pairs of bit lines (BL, XBL), a plurality of word lines WL and a plurality of memory cells 100; a decoder 104 for decoding address information to activate one of the plurality of word lines WL in accordance with the address information; precharge circuits 105 for setting each of the plurality of pair of bit lines (BL, XBL) to a predetermined precharge potential; sense amplifiers 110; and potential difference transmission circuits 109 provided between the memory cell array 101 and the sense amplifiers 110. The potential difference transmission circuits 109 hold a potential difference V.sub.d0 between respective pair of bit lines among the plurality of pairs of bit lines (BL, XBL) and transmit the held potential difference V.sub.d0 between the pair of bit lines to a respective sense amplifier 110. The sense amplifier 110 amplifies the potential difference V.sub.d0 between the pair of bit lines transmitted by the potential difference transmission circuit 109 so as to output the data stored in a corresponding memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.