Synchronous semiconductor memory device operable in a plurality of data write operation modes
US5892730A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Dec 1, 1997 |
| Grant date | Apr 6, 1999 |
| Priority date | — |
| Expiry date | Dec 1, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous semiconductor memory device can achieve either of a pipelined mode and a prefetch mode with one chip. In accordance with CAS (column address strobe) latency 4 instructing signal MCL4 stored in a mode register, a sequence of generation of control signals from a control signal generating circuit is set to either the pipelined mode or the prefetch mode. A mode switching circuit merely switches reset timings of a write buffer in accordance with a CAS latency. Therefore, the internal data write mode can be easily switched in accordance with an operation environment, and the synchronous semiconductor memory device can implement multiple data write modes with one chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.