Buffer control system
US5892762A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 1996 |
| Grant date | Apr 6, 1999 |
| Priority date | — |
| Expiry date | May 22, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A buffer control system is a system for implementing both a priority control process and a shaping process of cells with a hardware configuration of a small size in a network routing fixed-length packets which are respectively composed of transfer data and control information added to the transfer data, and to which priority information is assigned, according to the control information. If a cell written to an empty area of a cell buffer is a prioritized cell, and its expected output time is a time slot, an address where the cell is stored in the cell buffer is arranged in a time slot in a prioritized cell entry memory. When it reaches the time to read the cell stored in the time slot, the address stored in the time slot is written to an output list chain, and the cell is read from that address. The empty area of the buffer is managed using a free list chain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.