System and method for improving channel hardware performance for an array controller
US5893138A · kind A · utility
46Cited by
13References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1995 |
| Grant date | Apr 6, 1999 |
| Priority date | — |
| Expiry date | Oct 2, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an array controller for controlling the transfer of data from a host system to an array of data storage devices, comprising a processor connected via a local bus to a data buffer in which data is staged during said transfer. The array controller is provided with a buffer controller for controlling the operation of the buffer and is further provided with channel hardware for manifesting a plurality of data channels, selectable by the local bus address, over which data is transferred in and out of the data buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.