Routing for integrated circuits
US5894142A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1996 |
| Grant date | Apr 13, 1999 |
| Priority date | — |
| Expiry date | Dec 11, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/90
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Signals are routed within a routing channel between a first logic block and a second logic block. A power signal within a power conductor is routed as part of a bottom layer of the routing channel. The bottom layer is located above a substrate for the integrated circuit. A ground signal is also routed within a ground conductor as part of the bottom layer of the routing channel. Data lines are routed in a top layer of the routing channel. The data lines carry data signals within the routing channel. Connection lines are routed within a middle layer of the routing channel. The middle layer is between the bottom layer of the routing channel and the top layer of the routing channel. The connecting lines connect a subset of the data lines in the top layer, the ground conductor in the bottom layer and the power conductor in the bottom layer to the first logic block and to the second logic block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.